IA32 EFER: Difference between revisions
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Created page with "MSR <code>0xc0000080</code> – <code>IA32_EFER</code> : If (CPUID.80000001H:EDX.[20] || CPUID.80000001H:EDX.[29]) {| class="wikitable" ! Bit ! Name ! Label ! Ops ! Description |-|- | 0 | SYSCALL Enable | IA32_EFER.SCE | R/W | Enables SYSCALL/SYSRET instructions in 64-bit mode. |- | 1 |rowspan=7 colspan=4| Reserved |- | 2 |- | 3 |- | 4 |- | 5 |- | 6 |- | 7 |- | 8 | IA-32e Mode Enable | IA32_EFER.LME | R/W | Enables IA-32e mode operation. |- | 9 |colspan=4| Reserved |-..." |
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MSR <code>0xc0000080</code> – <code>IA32_EFER</code> | MSR <code>0xc0000080</code> – <code>IA32_EFER</code> | ||
: | : Usable if (CPUID.80000001H:EDX.[20] || CPUID.80000001H:EDX.[29]) | ||
{| class="wikitable" | {| class="wikitable" | ||
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| R/W | | R/W | ||
| | | | ||
|- | |||
|⋮ | |||
| colspan="4" |Reserved | |||
|} | |} | ||
From Intel SDM [https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html] | From Intel SDM [https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html] | ||
{{Page lang|en}} | |||
[[Category:Notes]] | |||
Latest revision as of 22:36, 20 February 2025
MSR 0xc0000080 – IA32_EFER
- Usable if (CPUID.80000001H:EDX.[20] || CPUID.80000001H:EDX.[29])
| Bit | Name | Label | Ops | Description |
|---|---|---|---|---|
| 0 | SYSCALL Enable | IA32_EFER.SCE | R/W | Enables SYSCALL/SYSRET instructions in 64-bit mode. |
| 1 | Reserved | |||
| 2 | ||||
| 3 | ||||
| 4 | ||||
| 5 | ||||
| 6 | ||||
| 7 | ||||
| 8 | IA-32e Mode Enable | IA32_EFER.LME | R/W | Enables IA-32e mode operation. |
| 9 | Reserved | |||
| 10 | IA-32e Mode Active | IA32_EFER.LMA | R | Indicates IA-32e mode is active when set. |
| 11 | Execute Disable Bit Enable | IA32_EFER.NXE | R/W | |
| ⋮ | Reserved | |||
From Intel SDM [1]