Template:x86 protected mode interrupts: Difference between revisions

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Created page with "<noinclude> Originally created for Wikipedia. [https://en.wikipedia.org/w/index.php?title=Template:X86_protected_mode_interrupts&oldid=1283313564] This table contains information collected from the ''Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide'' revision from April 2022. == Interrupt table == </noinclude> {| class="wikitable sortable" |+ x86 Interrupt descriptor table items<ref>''Intel..."
 
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{| class="wikitable sortable"
{| class="wikitable sortable"
|+ x86 [[Interrupt descriptor table]] items<ref>''Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide'', April 2022</ref> <span class="plainlinks" style="font-weight: normal">&#x5b;[https://wiki.jwo.cz/wiki/Template:X86_protected_mode_interrupts?action=edit edit table]]</span>
|+ x86 Interrupt descriptor table items<ref>''Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide'', April 2022</ref> <span class="plainlinks" style="font-weight: normal">&#x5b;[https://wiki.jwo.cz/wiki/Template:x86_protected_mode_interrupts?action=edit edit table]]</span>
|-
|-
! class="unsortable" colspan="2" | {{abbr|Int. №|Interrupt number}}
! class="unsortable" colspan="2" | {{abbr|Int. №|Interrupt number}}
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! class="unsortable" rowspan="2" style="text-align: left" | Source
! class="unsortable" rowspan="2" style="text-align: left" | Source
|-
|-
! class="unsortable" | [[Hexadecimal|{{abbr|hex|Hexadecimal}}]]
! class="unsortable" | {{abbr|hex|Hexadecimal}}
! [[Decimal|{{abbr|dec|Decimal}}]]
! {{abbr|dec|Decimal}}
|-
|-
| 0x00
| 0x00
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| Fault  
| Fault  
| {{t/no|No}}
| {{t/no|No}}
| [[Division by zero|Divide Error]]
| Divide Error  
| DIV and IDIV instructions.  
| DIV and IDIV instructions.  
|-
|-
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| {{t/no|No}}
| {{t/no|No}}
| Debug Exception  
| Debug Exception  
| Instruction, data, and I/O [[Breakpoint|breakpoints]]; [[Trap flag|single-step]]; and others.  
| Instruction, data, and I/O breakpoints; single-step; and others.  
|-
|-
| 0x02
| 0x02
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| {{t/no|No}}
| {{t/no|No}}
| NMI Interrupt  
| NMI Interrupt  
| [[Non-binary gender|Nonmaskable external interrupt]].  
| Nonmaskable external interrupt.  
|-
|-
| 0x03
| 0x03
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| Trap  
| Trap  
| {{t/no|No}}
| {{t/no|No}}
| [[Breakpoint]]
| Breakpoint  
| [[INT3]] instruction.  
| INT3 instruction.  
|-
|-
| 0x04
| 0x04
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| Trap  
| Trap  
| {{t/no|No}}
| {{t/no|No}}
| [[Integer overflow|Overflow]]
| Overflow  
| INTO instruction.  
| INTO instruction.  
|-
|-
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| Fault  
| Fault  
| {{t/no|No}}
| {{t/no|No}}
| [[Illegal opcode|Invalid Opcode]] (Undefined Opcode)  
| Invalid Opcode (Undefined Opcode)  
| UD instruction or reserved opcode.  
| UD instruction or reserved opcode.  
|-
|-
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| Fault  
| Fault  
| {{t/no|No}}
| {{t/no|No}}
| Device Not Available ([[X87|No Math Coprocessor]])  
| Device Not Available (No Math Coprocessor)  
| Floating-point or WAIT/FWAIT instruction.  
| Floating-point or WAIT/FWAIT instruction.  
|-
|-
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| Abort  
| Abort  
| {{t/yes|Yes (zero)}}
| {{t/yes|Yes (zero)}}
| [[Double fault|Double Fault]]
| Double Fault  
| Any instruction that can generate an exception, an {{abbr|NMI|Non-maskable interrupt}}, or an {{abbr|INTR|external interrupt}}.  
| Any instruction that can generate an exception, an {{abbr|NMI|Non-maskable interrupt}}, or an {{abbr|INTR|external interrupt}}.  
|-
|-
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| Fault  
| Fault  
| {{t/no|No}}
| {{t/no|No}}
| [[X87|Coprocessor]] Segment Overrun (reserved)  
| Coprocessor Segment Overrun (reserved)  
| Floating-point instruction.
| Floating-point instruction.
|-
|-
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| Fault  
| Fault  
| {{t/yes|Yes}}
| {{t/yes|Yes}}
| Invalid [[Task state segment|TSS]]
| Invalid TSS  
| Task switch or [[Task state segment|TSS]] access.  
| Task switch or TSS access.  
|-
|-
| 0x0B
| 0x0B
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| Fault  
| Fault  
| {{t/yes|Yes}}
| {{t/yes|Yes}}
| [[X86 memory segmentation|Segment]] Not Present  
| Segment Not Present  
| Loading [[X86 memory segmentation|segment registers]] or accessing system segments.  
| Loading segment registers or accessing system segments.  
|-
|-
| 0x0C
| 0x0C
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| Fault  
| Fault  
| {{t/yes|Yes}}
| {{t/yes|Yes}}
| [[General protection fault|General Protection]]
| General Protection  
| Any memory reference and other protection checks.  
| Any memory reference and other protection checks.  
|-
|-
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| Fault  
| Fault  
| {{t/yes|Yes}}
| {{t/yes|Yes}}
| [[Page fault|Page Fault]]
| Page Fault  
| Any memory reference.  
| Any memory reference.  
|-
|-
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| Fault  
| Fault  
| {{t/no|No}}
| {{t/no|No}}
| [[x87 FPU]] Floating-Point Error (Math Fault)  
| x87 FPU Floating-Point Error (Math Fault)  
| [[x87 FPU]] floating-point or WAIT/FWAIT instruction.  
| x87 FPU floating-point or WAIT/FWAIT instruction.  
|-
|-
| 0x11
| 0x11
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| Fault  
| Fault  
| {{t/no|No}}
| {{t/no|No}}
| [[Single instruction, multiple data|SIMD]] Floating-Point Exception  
| SIMD Floating-Point Exception  
| [[Streaming SIMD Extensions|SSE]]/[[SSE2]]/[[SSE3]] floating-point instructions
| SSE/SSE2/SSE3 floating-point instructions
|-
|-
| 0x14
| 0x14

Latest revision as of 23:04, 1 April 2025

Originally created for Wikipedia. [1]

This table contains information collected from the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide revision from April 2022.

Interrupt table

x86 Interrupt descriptor table items[1] [edit table]
Int. № Mnem. Type Err. code Name Source
hex dec
0x00 0 #DE Fault No Divide Error DIV and IDIV instructions.
0x01 1 #DB Trap No Debug Exception Instruction, data, and I/O breakpoints; single-step; and others.
0x02 2 NMI Interrupt No NMI Interrupt Nonmaskable external interrupt.
0x03 3 #BP Trap No Breakpoint INT3 instruction.
0x04 4 #OF Trap No Overflow INTO instruction.
0x05 5 #BR Fault No BOUND Range Exceeded BOUND instruction.
0x06 6 #UD Fault No Invalid Opcode (Undefined Opcode) UD instruction or reserved opcode.
0x07 7 #NM Fault No Device Not Available (No Math Coprocessor) Floating-point or WAIT/FWAIT instruction.
0x08 8 #DF Abort Yes Double Fault Any instruction that can generate an exception, an NMI, or an INTR.
0x09 9 N/A Fault No Coprocessor Segment Overrun (reserved) Floating-point instruction.
0x0A 10 #TS Fault Yes Invalid TSS Task switch or TSS access.
0x0B 11 #NP Fault Yes Segment Not Present Loading segment registers or accessing system segments.
0x0C 12 #SS Fault Yes Stack-Segment Fault Stack operations and SS register loads.
0x0D 13 #GP Fault Yes General Protection Any memory reference and other protection checks.
0x0E 14 #PF Fault Yes Page Fault Any memory reference.
0x0F 15 N/A No N/A
0x10 16 #MF Fault No x87 FPU Floating-Point Error (Math Fault) x87 FPU floating-point or WAIT/FWAIT instruction.
0x11 17 #AC Fault Yes Alignment Check Any data reference in memory.
0x12 18 #MC Abort No Machine Check Error codes (if any) and source are model dependent.
0x13 19 #XM Fault No SIMD Floating-Point Exception SSE/SSE2/SSE3 floating-point instructions
0x14 20 #VE Fault No Virtualization Exception EPT violations
0x15 21 #CP Fault Yes Control Protection Exception RET, IRET, RSTORSSP, and SETSSBSY instructions can generate this exception. When CET indirect branch tracking is enabled, this exception can be generated due to a missing ENDBRANCH instruction at target of an indirect call or jump.
0x16
⋮
0x1f 		22
⋮
31 		??? N/A
0x20
⋮
0xff 		32
⋮
255 		N/A Interrupt No N/A External interrupts.
  1. ↑ Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide, April 2022
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